This invention relates to semiconductor packaging and, particularly, to wire bond interconnection.
Wire bonding provides a widely accepted means for interconnecting a semiconductor device with the circuitry in which the device is used. Particularly, for example, wire bonds are used to make connections between pads at the active surface of the die and bond sites on a lead frame or on lead fingers on a substrate.
Developments in semiconductor processing have provided increasing numbers and densities of elements in the semiconductor die, and, accordingly, higher numbers of smaller and more closely arranged pads for interconnection of the die with the environment in which it used. A typical die pad pitch may be, for example, about 45-50 μm.
In practice, owing in part to process limitations, the densities of lead fingers on a typical substrate are significantly greater, and the lead finger pitch in a conventional substrate may typically be about three times greater than the die pad pitch. As a result, the wires must “fan out” from the die pads to bonds sites on the lead fingers.
The circuitry in the metal layer on a substrate, including traces and bond fingers, is ordinarily formed by masking, patterning and etching a metal layer (such as copper, for example) on the substrate dielectric. Usually the patterned etch results in traces having generally trapezoidal cross-sections, so that the “flat” or “pad” on which the stitch bond is formed on the bond fingers, for example, is narrower than the base, next to the substrate. Typically the flat on a conventional lead finger is significantly wider than the stitch bond that is to be formed upon it, and the flat on a conventional lead finger may be about 2-3 times as wide as the wire diameter. A typical flat width may be about 40 μm, for example, and because the cross-section of the lead finger is typically trapezoidal (the flat being narrower than the base), the width of the lead finger at the substrate dielectric that carries it is somewhat greater. Moreover, usually, where the circuitry is copper, for example, the patterned bond fingers are plated with nickel (to a thickness about 5-10 μm) and gold (to a thickness about 0.5 μm), adding further to the overall width of the bond fingers. Plating debris may be left on the dielectric adjacent the plated lead fingers, requiring additional separation between adjacent lead fingers, to avoid electrical shorts. Owing to these and other various processing limitations, the design distance between adjacent traces or bond fingers cannot be reduced below a practical limit, which may typically be about 45 μm.
As a result of these requirements and limitations, in a conventional substrate having plated copper traces the lead finger pitch may be about 130 μm, for example. Where the die pad pitch is about 50 μm, for example, the wire bonds from a row of pads along one edge of the die must fan out to a row of lead fingers that may be nearly three times as wide as the row of die pads. This requires that the substrate be much larger than the die, and that the wires be very long. Greater substrate size and longer wires results in greater materials and processing costs. Moreover, where radio frequency (“rf”) signals are to be carried between the die and the substrate, longer wires are undesirable because long wires carrying rf signals can cause electromagnetic interference with nearby wires or circuitry.
It is desirable, therefore, to reduce the bond finger pitch as much as is practicable.